The day before yesterday I had finally finished firmware in VHDL which is burned into Altera CPLDs in my design. Now all works fine, including surrounding digital schematics.
Unfortunately, I spent about two months on this part of project instead of planned four weeks. The reason is lack of attention during initial schematics development and VHDL program writing. Little logical error in VHDL program and lack of thorough test simulations caused me to solder several wires to key logic nets of the design under consideration, connect them to special debug connector and examine its pins with oscilloscope. Physical layout of the two mezzanine PCBs does not allow to access all logic nets directly with oscilloscope probes. At the end, error in firmware was found and fixed, but at price of extra time and nerves.
After VHDL firmware was fixed, the device still did not function as it should. The reason traced to be a subtle difference in my schematics in comparison with third-party device to which my design should be compatible. My schematics was right, but incompatible with third-party software from manufacturer of that device. This was fixed by means of one 0603 resitor and two equipment wires.
Finally, this part of device passed all tests.
The lesson learned is the impermissibility of neglecting thorough and attentive requirement analysis and creating simulation tests during initial design phase.
